UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 682

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
21.6 STOP Mode/Low-Voltage STOP Mode
21.6.1 Setting and operation status
in the normal operation mode. The low-voltage STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01
or 11 and setting the PSC.STP bit to 1 after setting the REGOVL0 register to 01H in normal operation mode.
CPU and the on-chip peripheral functions is stopped.
retained. Clock supply to the CPU and the on-chip peripheral functions is stopped, but the subclock oscillator continues
operating. In the STOP mode, CSIBn and UARTA0 that can operate with the external clock continue operating. In the
low-voltage STOP mode, stop supply of the external clock to CSIBn and UARTA0 (n = 0 to 4).
STOP mode.
lower than the IDLE2 mode. If the subclock oscillator, internal oscillator, low-voltage detector (LVI), and external clock are
not used, the power consumption can be minimized with only leakage current flowing.
lowered.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1
In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the
As a result, program execution stops, and the contents of the internal RAM before the STOP mode was set are
Table 21-8 shows the operating status in the STOP mode and Table 21-9 shows the operating status in the low-voltage
Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level
The power consumption decreases further in the low-voltage STOP mode because the voltage of the regulator is
Be sure to set the low-voltage STOP mode in the following procedure.
(1) Procedure for setting “normal mode” → “low-voltage STOP mode”
Make the following setting in the normal operation mode (while the main clock is operating).
<1> Stop the functions that are specified to be stopped in Table 21-9 Operating Status in Low-Voltage STOP
<2> Disable the DMA operation.
<3> • Disable the maskable interrupt by the DI instruction.
<4> Write C9H (enabling data) to the REGPR register.
<5> Write 01H to the REGOVL0 register.
<6> Write 00H (protection data) to the REGPR register.
<7> As necessary, enable the maskable interrupt, NMI interrupt, or INTWDT2 interrupt by the EI instruction
<8> Set the STOP mode.
Mode.
Be especially sure to stop the following functions, because they are signals from external sources.
• Stop the SCKBn input clock when the SCKBn input clock to CSIBn is selected (n = 0 to 4).
• Stop the ASCKA0 input clock when the ASCKA0 input clock to UARTA0 is selected.
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (stop watchdog timer 2 or set a mode other
At this time, the output voltage of the regulator is at the normal level.
(restore the settings <2> and <3>, above).
In the STOP mode, the output voltage of the regulator drops, decreasing the current consumption to an
extremely low level.
than the INTWDT2 mode. Create a status in which the INTWDT2 signal is not generated immediately after
watchdog timer 2 has been cleared).
PSMR.PSM1, PSMR.PSM0 bits = 01 or 11
PSC.STP bit = 1
CHAPTER 21 STANDBY FUNCTION
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