UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 660

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UPD70F3735GC-GAD-AX

Manufacturer Part Number
UPD70F3735GC-GAD-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GC-GAD-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0)
Remark
The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI
pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the port
Caution Be sure to clear the INTF0n and INTR0n bits to 00 when these registers are not used as the NMI
Remark
INTF0n
For how to specify a valid edge, see Table 19-3.
function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 00, and then
set the port mode.
or INTP0 to INTP3 pins.
n = 2:
n = 3 to 6: Control of INTP0 to INTP3 pins
INTR0
0
0
1
1
INTF0
After reset: 00H
Control of NMI pin
INTR0n
0
0
0
1
0
1
R/W
INTF06
INTR06
INTP3
INTP3
Table 19-3. Valid Edge Specification
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
No edge detected
Rising edge
Falling edge
Both rising and falling edges
Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H
INTF05
INTR05
INTP2
INTP2
INTF04
INTR04
INTP1
INTP1
Valid Edge Specification (n = 2 to 6)
INTF03
INTR03
INTP0
INTP0
INTF02
INTR02
NMI
NMI
0
0
0
0
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