UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 632

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Maskable
Type
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same time.
Interrupt
Classification
Default
Priority
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
46
47
48
49
50
51
52
53
54
INTTP5OV
INTTP5CC0
INTTP5CC1
INTTM0EQ0 TMM0 compare match
INTCB0R/
INTIIC1
INTCB0T
INTCB1R
INTCB1T
INTCB2R
INTCB2T
INTUA0R
INTUA0T
INTUA1R
INTUA1T
INTUA2R/
INTIIC0
INTUA2T
INTAD
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTKR
INTWTI
INTWT
Name
The highest priority is 0.
The priority order of non-maskable interrupt is INTWDT2 > NMI.
TMP5 overflow
TMP5 capture 0/compare 0 match
TMP5 capture 1/compare 1 match
CSIB0 reception completion/
CSIB0 reception error/
IIC1 transfer completion
CSIB0 consecutive transmission
write enable
CSIB1 reception completion/
CSIB1 reception error
CSIB1 consecutive transmission
write enable
CSIB2 reception completion/
CSIB2 reception error
CSIB2 consecutive transmission
write enable
UARTA0 reception completion
UARTA0 consecutive transmission
enable
UARTA1 reception completion/
UARTA1 reception error
UARTA1 consecutive transmission
enable
UARTA2 reception completion/
IIC0 transfer completion
UARTA2 consecutive transmission
enable
A/D conversion completion
DMA0 transfer completion
DMA1 transfer completion
DMA2 transfer completion
DMA3 transfer completion
Key return interrupt
Watch timer interval
Watch timer reference time
Table 19-1. Interrupt Source List (2/3)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Trigger
TMP5
TMP5
TMP5
TMM0
CSIB0/
IIC1
CSIB0
CSIB1
CSIB1
CSIB2
CSIB2
UARTA0
UARTA0
UARTA1
UARTA1
UARTA/
IIC0
UARTA2
A/D
DMA
DMA
DMA
DMA
KR
WT
WT
Generating
Unit
0250H
0260H
0270H
0290H
02A0H
02B0H
02C0H
02D0H
02E0H
0310H
0320H
0330H
0340H
0350H
0360H
0370H
0380H
0390H
03A0H
03B0H
03C0H
03D0H
03E0H
0280H
Exception
Code
00000250H nextPC
00000260H nextPC
00000270H nextPC
00000280H nextPC
00000290H nextPC
000002A0H nextPC
000002B0H nextPC
000002C0H nextPC
000002D0H nextPC
000002E0H nextPC
00000310H nextPC
00000320H nextPC
00000330H nextPC
00000340H nextPC
00000350H nextPC
00000360H nextPC
00000370H nextPC
00000380H nextPC
00000390H nextPC
000003A0H nextPC
000003B0H nextPC
000003C0H nextPC
000003D0H nextPC
000003E0H nextPC
Address
Handler
Restored
PC
Page 616 of 816
TP5OVIC
TP5CCIC0
TP5CCIC1
TM0EQIC0
CB0RIC/
IICIC1
CB0TIC
CB1RIC
CB1TIC
CB2RIC
CB2TIC
UA0RIC
UA0TIC
UA1RIC
UA1TIC
UA2RIC/
IICIC0
UA2TIC
ADIC
DMAIC0
DMAIC1
DMAIC2
DMAIC3
KRIC
WTIIC
WTIC
Interrupt
Register
Control