UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 322

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must
be written.
To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the
TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active
level to the TQ0CCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TQ0CCR0 register, and then write the
same value to the TQ0CCR1 register.
To change only the active level width (duty factor) of the PWM waveform, first set an active level to the
TQ0CCR2 and TQ0CCR3 registers and then set an active level to the TQ0CCR1 register.
To change only the active level width (duty factor) of the PWM waveform output by the TOQ01 pin, only the
TQ0CCR1 register has to be set.
To change only the active level width (duty factor) of the PWM waveform output by the TOQ02 and TOQ03 pins,
first set an active level width to the TQ0CCR2 and TQ0CCR3 registers, and then write the same value to the
TQ0CCR1 register.
After data is written to the TQ0CCR1 register, the value written to the TQ0CCRm register is transferred to the
CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared
with the 16-bit counter.
To write the TQ0CCR0 to TQ0CCR3 registers again after writing the TQ0CCR1 register once, do so after the
INTTQ0CC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined
because timing of transferring data from the TQ0CCRm register to the CCRm buffer register conflicts with
writing the TQ0CCRm register.
Remark
m = 0 to 3
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Page 306 of 816