UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 706

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
22.3.4 Operation after reset release
option byte setting. For details, see CHAPTER 27 OPTION BYTE). Is secured, and the CPU starts program execution.
clock.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
After the reset is released, the main clock starts oscillation and oscillation stabilization time (differs depending on the
WDT2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source
(1) Emergent operation mode
Internal oscillation
Internal oscillation
If an anomaly occurs in the main clock before oscillation stabilization time is secured, the WDT2 overflows before
executing the CPU program. At this time, the CPU starts program execution by using the internal oscillation clock
as the source clock.
The CPU operation clock states can be checked with the CPU operation clock status register (CCLS).
V850ES/JF3-L
V850ES/JF3-L
Clock monitor
Clock monitor
Main clock
Main clock
WDT2
WDT2
clock
clock
Operation
Operation
Reset
stops
Reset
stops
Figure 22-5. Operation After Reset Release
Figure 22-6. Operation After Reset Release
Counting of oscillation stabilization time
Counting of oscillation stabilization time
Operation stops
Operation in progress
Operation in progress
Operation stops
CHAPTER 22 RESET FUNCTIONS
WDT overflows
Normal operation (f
Emergency mode
(f
Operation in progress (re-count)
CPU
Operation in progress
= internal oscillation clock)
CPU
= Main clock)
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