UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 742
UPD70F3735GC-GAD-AX
Manufacturer Part Number
UPD70F3735GC-GAD-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3735GC-GAD-AX.pdf
(835 pages)
Specifications of UPD70F3735GC-GAD-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD70F3735GC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JF3-L
28.4.6 Pin connection
programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory
programming mode.
as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the
status immediately after a reset.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
When performing on-board writing, mount a connector on the target system to connect to the dedicated flash
In the flash memory programming mode, all the pins not used for flash memory programming become the same status
(1) FLMD0 pin
(2) FLMD1 pin
Caution If the V
In the normal operation mode, input a voltage of V
mode, supply a write voltage of V
Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of V
be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 28.5.5 (1)
FLMD0 pin.
When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When V
the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an
example of the connection of the FLMD1 pin.
immediately after reset, isolate this signal.
DD
signal is input to the FLMD1 pin from another device during on-board writing and
V850ES/JF3-L
V850ES/JF3-L
FLMD0
Figure 28-10. FLMD0 Pin Connection Example
Figure 28-11. FLMD1 Pin Connection Example
FLMD1
DD
level to the FLMD0 pin.
Dedicated flash programmer connection pin
Pull-down resistor (R
Pull-down resistor (R
SS
level to the FLMD0 pin. In the flash memory programming
Other device
FLMD0
FLMD1
)
)
CHAPTER 28 FLASH MEMORY
DD
is supplied to the FLMD0 pin,
Page 726 of 816
DD
level must
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