UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 735

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
For details, refer to the PG-FP5 User’s Manual (U18865E).
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Signal Name
FLMD0
FLMD1
VDD
GND
CLK
RESET
SI/RxD
SO/TxD
SCK
HS
(3) CSIB0 + HS
The dedicated flash programmer outputs the transfer clock, and the V850ES/JF3-L operates as a slave.
When the PG-FP5 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JF3-L.
Note Wire these pins as shown in Figures 28-6 or connect them to GND via pull-down resistor on board.
Remark
Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board.
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
×: Does not have to be connected.
Output
Output
Output
Output
Input
Output
Output
Input
: Must be connected.
I/O
−
−
Figure 28-5. Communication with Dedicated Flash Programmer (CSIB0 + HS)
Dedicated flash
Table 28-5. Signal Connections of Dedicated Flash Programmer (PG-FP5)
programmer
Write enable/disable
Write enable/disable
V
Ground
Clock output to V850ES/JF3-L
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal for CSIB0 + HS
communication
DD
PG-FP5
voltage generation/voltage monitor
Pin Function
RESET
FLMD0
FLMD1
GND
SCK
V
SO
HS
SI
DD
FLMD0
FLMD1
V
V
X1, X2
RESET
SOB0/TXDA0
SIB0/RXDA0
SCKB0
PCM0
V850ES/JF3-L
DD
SS
Pin Name
FLMD0
FLMD1
V
RESET
SOB0
SIB0
SCKB0
PCM0
V
SS
DD
Note
UARTA0
CHAPTER 28 FLASH MEMORY
×
×
×
Note
Processing for Connection
V850ES/JF3-L
CSIB0
×
×
Note
CSIB0 + HS
Page 719 of 816
×
Note