UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 574

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UPD70F3735GC-GAD-AX

Manufacturer Part Number
UPD70F3735GC-GAD-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GC-GAD-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss)
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(1) When arbitration loss occurs during transmission of slave address data
(2) When arbitration loss occurs during transmission of extension code
ST
ST
Δ 2: IICSn register = 00000001B
IICCn.LRELn bit is set to 1 by software
Δ 2:
Remarks 1.
Remarks 1.
1: IICSn register = 01000110B (Example: When IICSn.ALDn bit is read during interrupt servicing)
1:
AD6 to AD0
AD6 to AD0
IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing)
IICSn register = 00000001B
2. n = 0, 1
2. n = 0, 1
Δ: Generated only when IICCn.SPIEn bit = 1
Δ: Generated only when SPIEn bit = 1
X: don’t care
: Always generated
: Always generated
R/W
R/W
1
ACK
ACK
1
D7 to D0
D7 to D0
ACK
ACK
D7 to D0
D7 to D0
ACK
ACK
SP
SP
Δ2
Δ2
CAPTER 17 I
Page 558 of 816
2
C BUS

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