UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 152

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

USB interface
25.3.4
25.3.5
25.3.6
152/293
Figure 55. FIFO pairing example (1/2 IN paired and 3/4 OUT paired)
Reading and writing FIFOs
There are a total of ten 64-byte FIFOs. Each of the five Endpoints has two FIFOs, one IN
FIFO for IN transactions and one OUT FIFO for OUT transactions. The FIFOs are
accessible by the CPU through a 64-byte segment in the XDATA space when the VISIBLE
Bit is set (see
accessible by the CPU but are still accessible by the SIE. The base address of the 64-byte
segment is specified by the USB Base Address High Register (see
and the USB Base Address Low Register (see
Bit is set, the FIFO that is accessible in the 64-byte XDATA space segment is the FIFO
selected by the USEL register. The USEL register contains two fields used for selecting the
accessible FIFO. The EP field determines the Endpoint selected and the DIR Bit selects the
IN or OUT FIFO associated with the Endpoint.
Accessing FIFO control registers, UCON, and USIZE
Each of the 10 Endpoint FIFOs has an associated USB Endpoint Control Register (UCON,
0F1H) and a USB FIFO Valid Size Register (USIZE, 0F2H). The USB Endpoint Select
Register (USEL) is not only used to select the Endpoint FIFO that is accessible in the
XDATA space, but also selects the associated Endpoint’s UCON and USIZE registers that
are accessible at SFR addresses 0F1H and 0F2H.
Accessing the setup command buffer
Setup Packets are sent from the host to a device’s Endpoint0 and consist of 8 bytes of
command data. When the SIE receives a Setup packet from the host, it stores the 8 bytes of
data in the Command Buffer. The command buffer is accessed via the indexed USB Setup
Interface
Engine
Serial
Table 80 on page
(not available)
(not available)
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint4
Endpoint4
Endpoint3
Endpoint2
Endpoint1
Endpoint0
P
a
e
d
P
a
e
d
i
r
i
r
Endpoint0 OUT FIFO
Endpoint1 OUT FIFO
Endpoint2 OUT FIFO
Endpoint3 OUT FIFO
Endpoint4 OUT FIFO
Endpoint0 IN FIFO
Endpoint4 IN FIFO
Endpoint3 IN FIFO
Endpoint2 IN FIFO
Endpoint1 IN FIFO
163). If the VISIBLE Bit is not set, the FIFOs are not
P
a
e
d
P
a
e
d
i
r
i
r
Table 86 on page
(not available)
(not available)
Endpoint2
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint4
Endpoint4
Endpoint3
Endpoint1
Endpoint0
Interface
Logic
FIFO
168). When the VISIBLE
Table 85 on page
XDATA
CTRL
USB SFRs
uPSD34xx
8032
MCU
AI10494
168)
R
S
F
B
u
s