UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 163

MCU 8BIT 8032 128KB FLASH 80TQFP

UPSD3433EB40U6

Manufacturer Part Number
UPSD3433EB40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433EB40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5660

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3433EB40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
UPSD3433EB40U6
Manufacturer:
ST
0
uPSD34xx
Table 80.
Bit 7
Bit
USB Control Register (UCTL)
The USB Control Register (see
FIFOs visible in the XDATA space and for generating a remote wakeup signal. Upon a
reset, the USB module is disabled and must be enabled by the CPU for communication
with the host over the USB.
7
6
5
4
3
2
1
0
WAKEUP
USB control register (UCTL 0ECh, reset value 00h)
VISIBLE
Symbol
USBEN
Bit 6
Bit 5
R/W
R/W
R/W
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
USB Enable
When this bit is set, the USB function is enabled and the SIE
responds to tokens from the host. When this bit is clear, the
USB function is disabled and does not respond to any tokens
from the host.
Note: A USB reset does not clear this bit. Disabling and
enabling the SIE using this bit resets part of the USB SIE state
machine and some of the bits in the USTA and UCON
registers.
USB FIFO VISIBLE
When this bit is set, the selected USB FIFO is accessible
(visible) in the XDATA space.
Remote Wakeup Enable
This bit forces a resume or “K” state on the USB data lines to
initiate a remote wake-up. The CPU is responsible for
controlling the timing of the forced resume that must be
between 10ms and 15ms. Setting this bit will not cause the
RESUMF Bit to be set.
Table
Bit 4
80) is used to enable the SIE, make the Endpoint
Bit 3
Definition
USBEN
Bit 2
VISIBLE
Bit 1
USB interface
WAKEUP
Bit 0
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