UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 93

MCU 8BIT 8032 128KB FLASH 80TQFP

UPSD3433EB40U6

Manufacturer Part Number
UPSD3433EB40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433EB40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5660

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3433EB40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
UPSD3433EB40U6
Manufacturer:
ST
0
uPSD34xx
Note:
1
Table 43.
The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact
same function as RCLK and TCLK.
Bit 7
TF2
Bit
7
6
5
4
3
2
1
0
T2CON: Timer 2 control register (SFR C8h, reset value 00h)
Symbol
RCLK
TCLK
CP/RL2
EXEN2
EXF2
EXF2
C/T2
Bit 6
TR2
TF2
(1)
(1)
RCLK
Bit 5
R/W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
Timer 2 flag, causes interrupt if enabled.
TF2 is set by hardware upon overflow. Must be cleared by
firmware. TF2 will not be set when either RCLK or TCLK =1.
Timer 2 flag, causes interrupt if enabled.
EXF2 is set when a capture or reload is caused by a negative
transition on T2X pin and EXEN2 = 1. EXF2 must be cleared
by firmware.
UART0 Receive Clock control.
When RCLK = 1, UART0 uses Timer 2 overflow pulses for its
receive clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is
used for its receive clock
UART0 Transmit Clock control.
When TCLK = 1, UART0 uses Timer 2 overflow pulses for its
transmit clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is
used for transmit clock
Timer 2 External Enable.
When EXEN2 = 1, capture or reload results when negative
edge on pin T2X occurs. EXEN2 = 0 causes Timer 2 to ignore
events at pin T2X.
Timer 2 run control.
1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off.
Counter or Timer function select.
When C/T2 = 0, function is timer, clocked by internal clock.
When C/T2 = 1, function is counter, clocked by signal sampled
on external pin, T2.
Capture/Reload.
When CP/RL2 = 1, capture occurs on negative transition at pin
T2X if EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs
when Timer 2 overflows, or on negative transition at pin T2X
when EXEN2=1. When RCLK = 1 or TCLK = 1, CP/RL2 is
ignored, and Timer 2 is forced to auto-reload upon Timer 2
overflow
TCLK
Bit 4
EXEN2
Bit 3
Definition
Standard 8032 timer/counters
Bit 2
TR2
Bit 1
C/T2
CP/RL2
Bit 0
93/293

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