UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 88

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

Standard 8032 timer/counters
20.3
88/293
period (12 / f
sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In
this case, an external clock signal on pins C0, C1, or T2 should have a duration longer than
one MCU machine cycle, t
explains how to estimate t
Table 41.
SFR, TCON
Timer 0 and Timer 1 share the SFR, TCON, that controls these timers and provides
information about them. See
Bits IE0 and IE1 are not related to Timer/Counter functions, but they are set by hardware
when a signal is active on one of the two external interrupt pins, EXTINT0 and EXTINT1. For
system information on all of these interrupts, see
Bits IT0 and IT1 are not related to Timer/Counter functions, but they control whether or not
the two external interrupt input pins, EXTINT0 and EXTINT1 are edge or level triggered.
Bit 7
TF1
Bit
7
6
5
4
3
2
1
0
OSC,
TCON: Timer control register (SFR 88h, reset value 00h)
Symbol
Bit 6
TR1
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
seconds). However, if MCU_CLK is divided by the SFR CCON0, then the
MACH_CYC
MACH_CYC
Bit 5
R/W
R,W
R,W
R,W
R,W
TF0
R
R
R
R
Table 41 on page
Timer 1 overflow interrupt flag. Set by hardware upon overflow.
Automatically cleared by hardware after firmware services the
interrupt for Timer 1.
Timer 1 run control. 1 = Timer/Counter 1 is on, 0 =
Timer/Counter 1 is off.
Timer 0 overflow interrupt flag. Set by hardware upon overflow.
Automatically cleared by hardware after firmware services the
interrupt for Timer 0.
Timer 0 run control. 1 = Timer/Counter 0 is on, 0 =
Timer/Counter 0 is off.
Interrupt flag for external interrupt pin, EXTINT1. Set by
hardware when edge is detected on pin. Automatically cleared
by hardware after firmware services EXTINT1 interrupt.
Trigger type for external interrupt pin EXTINT1. 1 = falling
edge, 0 = low-level
Interrupt flag for external interrupt pin, EXTINT0. Set by
hardware when edge is detected on pin. Automatically cleared
by hardware after firmware services EXTINT0 interrupt.
Trigger type for external interrupt pin EXTINT0. 1 = falling
edge, 0 = low-level
.
.
Section 19.5: Watchdog timer, WDT on page 84
Bit 4
TR0
88.
Bit 3
Table 16 on page
IE1
Definition
Bit 2
IT1
53, Interrupt Summary.
Bit 1
IE0
uPSD34xx
Bit 0
IT0