UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 62

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

MCU clock generation
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Table 22.
Table 23.
PLLM[4]
Bit 7
Bit 7
2:0
7:4
3:0
Bit
Bit
7
6
5
4
3
PLLM[3:0]
PLLD[3:0]
CCON0: Clock Control Register (SFR F9h, reset value 50h)
CCON1 PLL Control Register (SFR FAh, reset value 00h)
UPLLCE
PLLM[4]
Symbol
Symbol
DBGCE
CPUAR
CPUPS
PLLEN
PLLEN
Bit 6
Bit 6
PLLM[3:0]
UPLLCE
Bit 5
Bit 5
R/W
R,W
R,W
R,W
R,W
R,W
R,W
R/W
R,W
R,W
Upper bit of the 5-bit PLLM[4:0] Multiplier (Default: '0' for
PLLM = 00h)
PLL Enable
0 = Disable PLL operation
1 = Enable PLL operation (Default condition after reset)
USB Clock Enable
0 = USB clock is disabled (Default condition after reset)
1 = USB clock is enabled
Debug Unit Breakpoint Comparator Enable
0 = JTAG Debug Unit comparators are disabled
1 = JTAG Debug Unit comparators are enabled (Default
condition after reset)
Automatic MCU Clock Recovery
0 = There is no change of CPUPS[2:0] when an interrupt
occurs.
1 = Contents of CPUPS[2:0] automatically become 000b
whenever any interrupt occurs.
MCUCLK Pre-Scaler
000b: f
001b: f
010b: f
011b: f
100b: f
101b: f
110b: f
111b: f
Lower 4 bits of the 5-bit PLLM[4:0] Multiplier (Default after
reset: PLLM = 00h)
PLLM[4] is in the CCON0 Register.
4-bit PLL Divider (Default after reset: PLLD = 0h)
DBGCE
Bit 4
Bit 4
MCU
MCU
MCU
MCU
MCU
MCU
MCU
MCU
= f
= f
= f
= f
= f
= f
= f
= f
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
CPUAR
Bit 3
Bit 3
/2
/4
/8
/16
/32
/1024
/2048
(Default after reset)
Definition
Definition
Bit 2
Bit 2
PLLD[3:0]
CPUPS[2:0]
Bit 1
Bit 1
uPSD34xx
Bit 0
Bit 0