UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 241

MCU 8BIT 8032 128KB FLASH 80TQFP

UPSD3433EB40U6

Manufacturer Part Number
UPSD3433EB40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433EB40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5660

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3433EB40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
UPSD3433EB40U6
Manufacturer:
ST
0
uPSD34xx
Note:
28.5.51
1
Figure 88. Port D structure
Optional function on a specific Port D pin.
Power management
The PSD Module offers configurable power saving options, and also a way to manage
power to the SRAM (battery backup). These options may be used individually or in
combinations. A top level description for these functions is given here, then more detailed
descriptions will follow.
FROM DPLD
FROM AND-
INPUT BUS
FROM PLD
OR ARRAY
Zero-Power Memory: All memory arrays (Flash and SRAM) in the PSD Module are
built with zero-power technology, which puts the memories into standby mode (~ zero
DC current) when 8032 address signals are not changing. As soon as a transition
occurs on any address input, the affected memory “wakes up”, changes and latches its
outputs, then goes back to standby. The designer does not have to do anything special
TO POWER MANAGEMENT AND PLD INPUT BUS
DATA
8032
8032 RD
FROM DPLD EXTERNAL CHIP (ECSx)
PT OUTPUT ENABLE (.OE)
PSD MODULE RESET
8032
BITS
WR
DIRECTLY TO PLD INPUT BUS, NO IMC
DATA
8032
BIT
REGIS-
D
CSIOP
TERS
CLR
M
Q
P
D
B
U
X
Q
Q
TO POWER MANAGEMENT
REGISTERS
2
3
1
4
5
DIRECTION
ONE of 5
DATA OUT
(MCUI/O)
CSIOP
DIRECTION
DRIVE SELECT
DATA OUT
(MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
DRIVE
RESET
PSDsoft
CLKIN
CSI
1
2
PD1. PIN, PD2.PIN
O
M
U
T
P
U
T
U
X
(1)
(1)
OUTPUT
ENABLE
DRIVE TYPE SELECT
OUTPUT
ENABLE
OUTPUT
PIN
SLEW RATE
1 = FAST
NO
HYSTERESIS
BUFFER
CMOS
I/O PORT D
PIN INPUT
LOGIC
V
DD
V
PSD module
DD
PIN, PORT D
TYPICAL
AI09182
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