MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 100
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 100 of 314
- Download datasheet (5Mb)
External Interrupt (IRQ)
When an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of
these events occur:
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
100
$001D
Addr.
•
•
Vector fetch or software clear
Return of the interrupt pin to logic 1
IRQ
IRQ Status and Control
Register Name
Register (INTSCR)
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
DECODER
V
VECTOR
See page 102.
FETCH
DD
RESET
ACK
INTERNAL
PULLUP
DEVICE
Reset:
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Read:
Write:
Figure 8-1. IRQ Module Block Diagram
Figure 8-2. IRQ I/O Register Summary
V
MODE
DD
Bit 7
0
0
D
CK
CLR
= Unimplemented
Q
6
0
0
NOTE
5
0
0
IMASK
SYNCHRONIZER
4
0
0
VOLTAGE
DETECT
HIGH
IRQF
3
0
ACK
2
0
0
IRQF
Freescale Semiconductor
IMASK
1
0
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
MODE
Bit 0
0
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