MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 197

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TXINV — Transmit Inversion Bit
M — Mode (Character Length) Bit
WAKE — Wakeup Condition Bit
ILTY — Idle Line Type Bit
PEN — Parity Enable Bit
Freescale Semiconductor
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
This read/write bit determines whether ESCI characters are eight or nine bits long (See
Table
bit.
This read/write bit determines which condition wakes up the ESCI: a logic 1 (address mark) in the MSB
position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit.
This read/write bit determines when the ESCI starts counting logic 1s as idle character bits. The
counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then
a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning
the count after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
This read/write bit enables the ESCI parity function (see
inserts a parity bit in the MSB position (see
Table
1 = Transmitter output inverted
0 = Transmitter output not inverted
1 = 9-bit ESCI characters
0 = 8-bit ESCI characters
1 = Address mark wakeup
0 = Idle line wakeup
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
1 = Parity function enabled
0 = Parity function disabled
15-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit. Reset clears the M
15-3). Reset clears the PEN bit.
Setting the TXINV bit inverts all transmitted values including idle, break,
start, and stop bits.
M
0
1
0
0
1
1
Control Bits
PEN:PTY
0 X
0 X
1 0
1 1
1 0
1 1
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Table 15-5. Character Format Selection
Start Bits
1
1
1
1
1
1
Data Bits
8
9
7
7
8
8
NOTE
Character Format
Parity
None
None
Even
Even
Odd
Odd
Table
Stop Bits
15-5). When enabled, the parity function
1
1
1
1
1
1
Character Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
:
I/O Registers
197