MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 173
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one
interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the
example shown in
pending interrupt is serviced before the LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
See
14.3.2 Sources
The sources in
14.3.2.1 Software Interrupt (SWI) Instruction
The software interrupt (SWI) instruction causes a non-maskable interrupt.
14.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
Freescale Semiconductor
Figure 14-5
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
Table 14-1
for a flowchart depicting interrupt processing.
Figure
14-4, if an interrupt is pending upon exit from the interrupt service routine, the
INT1
INT2
can generate CPU interrupt requests.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 14-4
CLI
LDA
PSHH
PULH
RTI
PSHH
PULH
RTI
#$FF
.
Interrupt Recognition Example
NOTE
NOTE
INT1 INTERRUPT SERVICE ROUTINE
INT2 INTERRUPT SERVICE ROUTINE
BACKGROUND
ROUTINE
Interrupts
173
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