MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 148
![IC MCU 8BIT 8K FLASH 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC68908GZ8MFAE
Manufacturer Part Number
MC68908GZ8MFAE
Description
IC MCU 8BIT 8K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68908GZ8MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
M689xx
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 148 of 314
- Download datasheet (5Mb)
MSCAN08 Controller (MSCAN08)
12.13.6 MSCAN08 Receiver Interrupt Enable Register
WUPIE — Wakeup Interrupt Enable
RWRNIE — Receiver Warning Interrupt Enable
TWRNIE — Transmitter Warning Interrupt Enable
RERRIE — Receiver Error Passive Interrupt Enable
TERRIE — Transmitter Error Passive Interrupt Enable
BOFFIE — Bus-Off Interrupt Enable
OVRIE — Overrun Interrupt Enable
RXFIE — Receiver Full Interrupt Enable
148
1 = A wakeup event will result in a wakeup interrupt.
0 = No interrupt will be generated from this event.
1 = A receiver warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter warning status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receiver error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter error passive status event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A bus-off event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = An overrun event will result in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event will result in a receive interrupt.
0 = No interrupt will be generated from this event.
Address:
The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Read:
Write:
Figure 12-21. Receiver Interrupt Enable Register (CRIER)
WUPIE
$0505
Bit 7
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
RWRNIE
6
0
TWRNIE
5
0
NOTE
RERRIE
4
0
TERRIE
3
0
BOFFIE
2
0
OVRIE
1
0
Freescale Semiconductor
RXFIE
Bit 0
0
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