MC68908GZ8MFAE Freescale Semiconductor, MC68908GZ8MFAE Datasheet - Page 218

• Manufacturer Part Number: MC68908GZ8MFAE
• Description: IC MCU 8BIT 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68908GZ8MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: M689xx
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
16.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
The COP module is disabled if the RST pin or the IRQ pin is held at V
while the MCU is in monitor
TST
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, V
on the RST pin disables the COP module.
TST
OSC1
PORRST
4096
32
CYCLES
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 16-7. POR Recovery
16.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
16.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
16.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
voltage falls to the
DD
LVI
voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
TRIPF
(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST pin for all internal reset sources.
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
218
Freescale Semiconductor