MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 113

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

It is important to ensure that the Command (CBM) or AP control signal is connected to correct Address
line on the selected SDRAM. The address line used (or position) for the AP control signal is programmable
via bits 10:8 of the DACRx register.
In the case of a Samsung SDRAM (K4S641633D-G) which has 8 column address lines the AP address pin
is A10 (the address line used for the CBM/AP control signal may differ on other manufacturer devices).
We choose to use A19 for the CBM/AP control signal and connect it to A10 on the SDRAM. We then set
DACRx bits 10:8 to 010b which selects A19 as the CBM/AP mapping the Bank Select pins above this.
Note: for SDRAM’s with more column address lines the position of the CBM / AP control signal moves
up one address line in each case.
The following SDRAM pin connection tables are for use with 4Mbit, 16Mbit, 64Mbit or 128Mbit devices
only.
The following SDRAM pin connection tables are for use with 256 Mbit devices only.
For the 256 Mbyte SDRAM, there is the restriction that address line A20 cannot be output. (we need A24).
If you want consistent mapping of the D-RAM in ColdFire memory space, A20 must be sent to the
D-RAM. To get this done, the only way is to make sure the D-RAM controller outputs A20 during the CAS
phase on A21, and ensure address pin A21 is connected to a D-RAM pin that uses both row and column
address. In this case, there is only one such pin, and this is A8 (CAS8/RAS8). Also, to get the column
address on A21, the AP bit must be set above this, lowest we can set it is A22. So, AP must be connected
to A22. Bank addresses are then A23 and above. (Bank addresses need equal address during CAS and RAS
phase). The remaining 3 D-RAM ras-only address lines are connected to A9, A11 and A12.
Freescale Semiconductor
MCF5253 Pins
Row
Column
SDRAM Pins
MCF5253 Pins
Row
Column
SDRAM Pins
MCF5253 Pins
Row
Column
SDRAM Pins
)
A16
A0
16
Table 7-9. SDRAM Interface (16-Bit Port, 10-Column Address Lines
Table 7-7. SDRAM Interface (16-Bit Port, 8-Column Address Lines)
1
Table 7-8. SDRAM Interface (16-Bit Port, 9-Column Address Lines)
A16
A0
16
1
A16
A0
16
1
A15
A1
15
2
A15
A1
15
2
A15
15
A1
2
A14
A2
14
3
A14
A2
14
3
A14
14
A2
3
A13
MCF5253 Reference Manual, Rev. 1
A3
13
4
A13
A3
13
4
A13
13
A3
A12
4
A4
12
5
A12
12
A4
5
A12
A11
12
A4
A5
11
5
6
A11
A5
11
6
A10
A6
A11
10
A5
7
11
6
A10
A6
10
7
A9
A7
9
8
A10
A6
10
7
A9
A7
9
8
A17
A8
17
–
A9
A7
9
8
A18
A8
18
17
A18
A9
18
–
A18
18
17
A8
Synchronous DRAM Controller Module
A19
19
A9
–
A19
A10
19
–
A20
20
19
A9
A20
A10
20
–
A20
A11
20
–
A21
A10
21
A21
A11
–
21
A21
A12
–
21
–
A22
A11
A22
A12
22
A22
A13
22
–
–
22
–
A23
A13
A23
A12
A23
A14
23
23
23
–
–
–
7-9