MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 285

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive
data comprise 1 queue entry.
The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit
data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued
commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their
completion. Optionally, QIR[SPIFE] can be enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI Wrap
Register (QWR):
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the
following sequence repeats:
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each
command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,
QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables
wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless
another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to
show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written
at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a
transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and
QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.
Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations of phase
and polarity using QMR[CPHA, CPOL]. Data is transferred most significant bit (msb) first. The number
of bits transferred defaults to eight, but can be set to any value from 8 to 16 by writing a value into the
BITSE field of the command RAM, QCR[BITSE].
16.3.1
The QSPI contains an 80-byte block of static RAM that can be accessed by both the user and the QSPI.
This RAM does not appear in the MCF5253 memory map because it can only be accessed by the user
indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
Freescale Semiconductor
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1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
16 transmit data words (transfer RAM)
16 receive data words (transfer RAM)
The new queue pointer, QWR[NEWQP], points to the first command in the queue.
An internal queue pointer points to the command currently being executed.
The completed queue pointer, QWR[CPTQP], points to the last command executed.
The end queue pointer, QWR[ENDQP], points to the final command in the queue.
QSPI RAM
MCF5253 Reference Manual, Rev. 1
Queued Serial Peripheral Interface (QSPI) Module
16-3