MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 495

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Field
OCC
OCA
PEC
FPR
PE
6
5
4
3
2
Force Port Resume. This bit is not-EHCI compatible.
1 Resume detected/driven on port.
0 No resume (K-state) detected/driven on port
In host mode:
The software sets this bit to one to drive resume signaling. The controller sets this bit to one if a J-to-K transition is
detected while the port is in the Suspend state. When this bit transitions to a one a J-to-K transition is detected, the Port
Change Detect bit in the USBSTS register is also set. This bit will automatically change to zero after the resume
sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to
a zero after the resume duration is timed in the driver.
Note: When the controller owns the port, the resume sequence follows the defined sequence documented in the USB
This field is zero if Port Power(PP) is zero in host mode.
In Device mode:
After the device has been in Suspend State for 5 msec or more, the software must set this bit to one to drive resume
signaling before clearing. the controller will set this bit to one if a J-to-K transition is detected while the port is in the
Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a
one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is also set.
Over-current Change. The overcurrent detect function is not implemented. This bit will always read 0.
Over-current Active. The overcurrent detect function is not implemented. This bit will always read 0.
Port Enable/Disable Change.
For the root hub, this bit gets set only when a port is disabled due to disconnect on the port or due to the appropriate
conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). The software clears this by writing a
one to it.
In Device mode, the device port is always enabled. (This bit will be zero.)
1 Port disabled
0 No change
This field is zero if Port Power(PP) is zero.
Port Enabled/Disabled.
In host mode ports can be enabled only by the controller as a part of the reset and enable. The software cannot enable
a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by the host software.
Note: The bit status does not change until the port state actually changes. There may be a delay in disabling or enabling
When the port is disabled, (0) downstream propagation of data is blocked except for reset.
This field is zero if Port Power(PP) is zero in host mode.
In Device Mode, the device port is always enabled. (This bit will be one).
Table 24-27. Port Status and Control (PORTSC) Register Field Descriptions (continued)
Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this bit remains
a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect
because the port controller will time the resume operation clear the bit the port control state switches to HS or
FS idle.
a port due to other host and bus events.
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-33