MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 168

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
9.8
The MCF5253 has up to 57 programmable general-purpose outputs and up to 60 programmable
general-purpose inputs. Two groups of 32-bit registers control these GPIOs.
9-24
SHOWDATA Not used
EARBCTRL Legacy bit.
IARBCTRL
BCR24BIT
Bit Name
MBAR2 + $0x00C
MBAR2 + $0x0BC
MBAR2 + $0x0C0
MBAR2 + $0x0C0
MBAR2 + $0x0C4
MBAR2 + $0x0B0
MBAR2 + $0x0B4
MBAR2 + $0x0B8
MBAR2 + $0x000
MBAR2 + $0x004
MBAR2 + $0x008
General Purpose I/O
Address
0 Normal use
1 do not use
0 Normal use
1 do not use
as a 24-bit register. See
positions for the BCRs.
0 DMA BCRs function as 16-bit counters.
1 DMA BCRs function as 24-bit counters.
Legacy bit.
This bit controls the BCR and address mapping for the DMA. The bit allows the byte count register to be used
When using the park on current master setting, the first master to arbitrate
for the bus becomes the current master. The corresponding priority scheme
should be interpreted as the priority of the next master once the current
master finishes.
GPIO1-FUNCTION
GPIO-FUNCTION
GPIO-INT-CLEAR
GPIO-INT-STAT
GPIO1-READ
GPIO-INT-EN
GPIO-READ
GPIO1-OUT
GPIO-OUT
GPIO1-EN
GPIO-EN
Section 14.4, “DMA Memory Map and Register
Name
Table 9-25. Park Bit Descriptions
Table 9-26. General Purpose I/O
MCF5253 Reference Manual, Rev. 1
S
NOTE
Width
32
32
32
32
32
32
32
32
32
32
32
Description
gpio output value
gpio output value
gpio input value
gpio input value
interrupt enable
interrupt status
function select
function select
output enable
output enable
interrupt clear
Description
Definitions”
Reset Value
for memory maps and bit
0
0
0
–
0
0
0
–
–
0
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R