MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 131

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

terminate with error. The data bus can transfer byte or word-sized data. All 16 bits of the data bus are driven
during writes, regardless of port width or operand size.
8.2.5
Chip select CS1 is shared with QSPI_CS3 and GPIO28.
Power-on reset function of CS1/QSPI_CS3/GPIO28 is CS1
The function can be programmed in the Pin Configuration register.
Chip select CS0 shares with CS4.
Its default mode is dependent on the state of address pin A23 at power-on reset.
This is determined as follows:
During power-on reset, logic level of pins A23 and A20/A24 are sensed. A pull-up / pull-down resistor
should be connected between these pins and VDD or GND. Depending whether a pull-up or pull-down is
mounted, different options are selected.
When the address decode matches one of the chip select spaces, the MCF5253 processor will pull low the
appropriate chip select low indicating an external bus access.
CS2 is also available but is associated with the IDE read and write strobes IDE_DIOR and IDE_DIOW.
Configuration registers for CS3 are present but no hardware pin exists for this CS on the MCF5253.
However it is possible to program BUFENB2 via the CS3 registers.
8.2.6
The OE pin on the MCF5253 will be pulled low during any read cycle from a device selected by CS0, CS1,
CS2, or CS4.
8.3
These signals provide the external system interface for the MCF5253 (see
Freescale Semiconductor
Clock and Reset Signals
Chip Selects
Output Enable
A23
Pin
Signal Name
BCLK
RSTI
Pull-up: Boot from memory connected to CS0/CS4. CS0/CS4 function is CS0
Pull-down: Boot from on-chip boot ROM. CS0/CS4 function becomes CS4
Table 8-4. CF-Bus Signal Summary
MCF5253 Reference Manual, Rev. 1
Table 8-3. Chip Select Settings
Direction
Out
In
Description
Reset In
System Bus Clock Output (SYSCLK)
Description
Table
8-4).
Bus Operation
8-3