MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 535

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

H-Frame boundaries for the host controller correspond to increments of FRINDEX[13:3]. Micro-frame
numbers for the H-Frame are tracked by FRINDEX[2:0]. B-Frame boundaries are visible on the
high-speed bus via changes in the SOF token's frame number. Micro-frame numbers on the high-speed bus
are only derived from the SOF token's frame number (that is, the high-speed bus will see eight SOFs with
the same frame number value). H-Frames and B-Frames have the fixed relationship (that is, B-Frames lag
H-Frames by one micro-frame time) illustrated in
naturally aligned to H-Frames. The software schedules transactions for full- and low-speed periodic
endpoints relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly
the right time for the USB 2.0 hub periodic pipeline. As described in
Register (FRINDEX),”
SOFV), which lags the FRINDEX register bits [13:3] by one micro-frame count.
the required relationship between the value of FRINDEX and the value of SOFV. This lag behavior can be
accomplished by incrementing FRINDEX[13:3] based on carry-out on the 7 to 0 increment of
FRINDEX[2:0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2:0].
The software is allowed to write to FRINDEX.
provides the requirements that the software should adhere when writing a new value in FRINDEX.
Freescale Semiconductor
Micro-Frames
HC Periodic
Figure 24-46. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
Schedule
HS Bus
Frames
7
0
SS
the SOF Value can be implemented as a shadow register (in this example, called
HC Periodic Schedule
Frame Boundaries
1
Full/Low-Speed
Interface Data Structure
Transaction
2
CS
H-Frame N
3
CS
MCF5253 Reference Manual, Rev. 1
B-Frame N
4
CS
5
CS
Section 24.6.3.4, “Frame Index Register (FRINDEX),”
6
Figure
7
0
24-46. The host controller's periodic schedule is
SS
1
Full/Low-Speed
Interface Data Structure
Transaction
HS/FS/LS Bus
Frame Boundaries
2
CS
H-Frame N+1
Section 24.6.3.4, “Frame Index
3
CS
B-Frame N+1
4
CS
5
CS
Table 24-64
Universal Serial Bus Interface
6
7
0
illustrates
1
2
24-73