MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 354

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

I
18.5.4
This status register is read-only with the exception of bit 1 (IIF) and bit 4 (IAL), which can be cleared by
software. All bits are cleared on reset except bit 7 (ICF) and bit 0 (RXAK), which are set (=1) at reset.
18-10
2
C Modules
MSTA
TXAK
RSTA
Field
MTX
IIEN
IEN
1–0
7
6
5
4
3
2
1 The I
0 The module is disabled, but registers can still be accessed.
If the I
The slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition
is detected. Master mode will not be aware that the bus is busy; therefore, if a start cycle is initiated, the current bus
cycle can become corrupt. This ultimately results in either the current bus master or the I
after which bus operation returns to normal.
1 Interrupts from the I
0 Interrupts from the I
At reset, the Master/Slave Mode Select Bit is cleared. When this bit is changed from 0 to 1, a START signal is
generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is
generated and the operation mode changes from master to slave.
MSTA is cleared without generating a STOP signal when the master loses arbitration.
1 Master Mode
0 Slave Mode
The Transmit/Receive Mode Select Bit selects the direction of master and slave transfers. When addressed as a
slave this bit should be set by software according to the SRW bit in the status register. In master mode, this bit should
be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
1 Transmit
0 Receive
The Transmit Acknowledge Enable bit specifies the value driven onto SDA during acknowledge cycles for both
master and slave receivers.
Writing this bit only applies when the I
1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)
0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data
Writing a 1 to the Repeat Start bit will generate a repeated START condition on the bus, provided it is the current bus
master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by
another master, will result in loss of arbitration.
1 Generate repeat start cycle
0 No repeat start
Reserved.
The I
I
2
C Interrupt Enable
also set.
I
2
C Status Registers (MBSR)
2
2
C Enable bit controls the software reset of the entire I
C module is enabled in the middle of a byte transfer, the interface behaves as follows:
2
C module is enabled. This bit must be set before any other MBCR bits have any effect.
2
2
C module are enabled. An I
C module are disabled. This does not clear any currently pending interrupt condition.
Table 18-5. MBCR Register Field Descriptions
MCF5253 Reference Manual, Rev. 1
2
C bus is a receiver, not a transmitter.
2
Description
C interrupt occurs provided the IIF bit in the status register is
2
C module.
2
C module losing arbitration,
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