MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 547

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

One queue head is used to manage the data stream for one endpoint. The queue head structure contains
static endpoint characteristics and capabilities. It also contains a working area from where individual bus
transactions for an endpoint are executed. Each qTD represents one or more bus transactions, which is
defined in the context of the EHCI specification as a transfer.
The general processing model for the host controller's use of a queue head is simple:
If the host controller encounters errors during a transaction, the host controller will set one of the error
reporting bits in the queue head's Status field. The Status field accumulates all errors encountered during
the execution of a qTD (that is, the error bits in the queue head Status field are sticky until the transfer
(qTD) has completed). This state is always written back to the source qTD when the transfer is complete.
On transfer (for example, buffer or halt conditions) boundaries, the host controller must auto-advance
(without software intervention) to the next qTD. Additionally, the hardware must be able to halt the queue
so no additional bus transactions will occur for the endpoint and the host controller will not advance the
queue.
24.9.10.1 Buffer Pointer List Use for Data Streaming with qTDs
A qTD has an array of buffer pointers, which is used to reference the data buffer for a transfer. The EHCI
specification requires that the buffer associated with the transfer be virtually contiguous. This means that
if the buffer spans more than one physical page, it must obey the following rules:
Figure 24-51
Freescale Semiconductor
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Read a queue head
Execute a transaction from the overlay area
Write back the results of the transaction to the overlay area
Move to the next queue head
The first portion of the buffer must begin at some offset in a page and extend through the end of
the page.
The remaining buffer cannot be allocated in small chunks scattered around memory. For each 4K
chunk beyond the first page, each buffer portion matches to a full 4K page. The final portion, which
may only be large enough to occupy a portion of a page, must start at the top of the page and be
contiguous within that page.
illustrates these requirements.
MCF5253 Reference Manual, Rev. 1
Universal Serial Bus Interface
24-85