MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 164

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
9.5.2.2
The SWIVR contains the 8-bit interrupt vector the SIM returns during an interrupt- acknowledge cycle in
response to a SWT-generated interrupt. The following register illustrates the SWIVR programming model.
The SWIVR is an 8-bit supervisor write-only register. This register is set to the uninitialized vector $0F at
system reset.
9-20
SWTAVAL
SWTA
Field
SWT
4–3
2
1
0
Table 9-18. System Protection Control Register (SYPCR) Field Descriptions (continued)
The Software Watchdog Timing Delay bits (along with the SWP bit) select the timeout period for the SWT as shown
in
Software Watchdog Transfer Acknowledge Enable
0 SWTA Transfer Acknowledge disabled.
1 SWTA Assert Transfer Acknowledge enabled.
After 1 SWT timeout period of the unacknowledged assertion of the SWT interrupt, the Software Watchdog Transfer
Acknowledge will assert, which allows SWT to terminate a bus cycle and allow the IACK to occur.
Software Watchdog Transfer Acknowledge Valid
0 SWTA Transfer Acknowledge has NOT occurred.
1 SWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
Reserved, should be cleared.
Table 9-19
Software Watchdog Interrupt Vector Register
If the SWP and SWT bits are modified to select a new software timeout,
users must peform the software service sequence ($55 followed by $AA
written to the SWSR) before the new timeout period takes effect.
. At system reset, the software watchdog timer is set to the minimum timeout period.
SWP
0
0
0
0
1
1
1
1
Table 9-19. SWT Timeout Period
MCF5253 Reference Manual, Rev. 1
SWT[1:0]
00
01
10
11
00
01
10
11
NOTE
Description
SWT TIMEOUT PERIOD
2
2
2
2
2
2
2
2
11
13
15
22
24
26
28
9
/ BCLK
/ BCLK
/ BCLK
/ BCLK
/ BCLK
/ BCLK
/ BCLK
/ BCLK
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