MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 596

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.11.3.2.2 Data Toggle Inhibit
This feature is for test purposes only and should never be used during normal device controller operation.
Setting the data toggle Inhibit bit active ('1') causes the USB_DR to ignore the data toggle pattern that is
normally sent and accept all incoming data packets regardless of the data toggle state.
In normal operation, the USB_DR checks the DATA0/DATA1 bit against the data toggle to determine if
the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller
for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device
controller assumes the packet was already received and discards the packet (not reporting it to the DCD).
To prevent the USB_DR from re-sending the same packet, the device controller will respond to the error
packet by acknowledging it with either an ACK or NYET response.
24.11.3.3 Device Operational Model For Packet Transfers
All transactions on the USB bus are initiated by the host and in turn, the device must respond to any request
from the host within the turnaround time stated in the USB 2.0 Specification.
A USB host will send requests to the USB_DR in an order that can not be precisely predicted as a single
pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the
order of packet requests is predictable when the endpoint number and direction is considered. For example,
if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can expect the host will send IN
requests to that endpoint. This USB_DR prepares packets for each endpoint/direction in anticipation of the
host request. The process of preparing the device controller to send or receive data in response to host
initiated transaction on the bus is referred to as ‘priming’ the endpoint. This term will be used throughout
the following documentation to describe the USB_DR operation so the DCD can be architected properly
use priming. Further, note that the term ‘flushing’ is used to describe the action of clearing a packet that
was queued for execution.
24.11.3.3.1 Priming Transmit Endpoints
Priming a transmit endpoint will cause the device controller to fetch the device transfer descriptor (dTD)
for the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it will be stored
in the dQH until the device controller completes the transfer described by the dTD. Storing the dTD in the
dQH allows the device controller to fetch the operating context needed to handle a request from the host
without the need to follow the linked list, starting at the dQH when the host request is received.
After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device
controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint
up to the maximum number of endpoints configured at device synthesis time.
After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUS
register. For a primed transmit endpoint, the device controller can respond to an IN request from the host
and meet the stringent bus turnaround time of High Speed USB.
Since only the leading data is stored in the device controller FIFO, it is necessary for the device controller
to begin filling in behind leading data after the transaction starts. The FIFO must be sized to account for
the maximum latency that can be incurred by the system memory bus.
MCF5253 Reference Manual, Rev. 1
24-134
Freescale Semiconductor