MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 212

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

IDE and Flash Media Interface
The processor interface sends commands to the interface shift register. One command instructs the
interface shift register to do one of the following:
After writing a command to the interface shift register, the processor needs to monitor TxBUFFEREMPTY
or RxBUFFERFULL, and read or write data to the interface as required.
During and after transmission of a command, the processor can monitor the Interface Shift Register status
by looking at some status signals.
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Transmit a packet of N bits to the Flash Media device. The number of bits N is programmable. It
is also programmable if bits 15:0, or bits 47:0 in SD wide bus mode, need to be replaced with a
valid CRC or not. CRC insertion is possible for Memory Stick data packet and SecureDigital data
packets. CRC insertion is not possible for SecureDigital command packets.
Receive a packet of N bits from the Flash Media device. The number of bits N is programmable.
After reception of all bits, the interface shift register will display on status line CRC_IS_0 if CRC
check was successful or not. CRC check is done for Memory Stick data packets and for
SecureDigital data packets. No CRC check is available for SD command packets.
Wait for an interrupt event from the Flash Media device.
When the transmit shift register is empty, new data is loaded from the TxBUFFERREG. If the
transmit buffer register is empty, the interface shift register will stop the SCLKOUT clock, and wait
for new data to be written in the TxBUFFERREG.
When the receive shift register is full, data is transferred to the RxBUFFERREG. If the receive
buffer register is full, the interface shift register will stop the SCLKOUT clock, and wait until the
RxBUFFERREG is read.
If the number of bits in the packet to send/receive from the Flash Media is greater than 32, multiple
longword transfers to the buffer register are needed. All of these, except the first, contain 32 packet
bits. The last data word for the transfer always contains packet bits 31-0, even if CRC transmit or
check is on.
If e.g. a 48-bit transfer is requested to the Flash Media, the first data word will contain 16 bits, the
second one will contain 32 bits. The first word is LSB aligned for receive data, MSB aligned for
transmit data.
This is also true if CRC insertion is involved. If a 4096 bit packet + 16 bit CRC need to be
transmitted to the Flash Media, 129 long-word transfers are needed. The first long-word will
contain packet bits 4095:4080, MSB aligned. The last longword will contain packet bits 15:0
padded with 16 zeros or ones. The padded value will be replaced with the CRC by the transmit
interface (if the interface is programmed to do so).
SHIFT_BUSY This signal is high while the data transmission is in progress.
INT_LEVEL During interrupt commands, a high on this signal indicates an interrupt event coming
from the Flash Media.
CRC_IS_0 After a read transmission is completed, this signal indicates if the packet CRC was 0 or
not.
BITCOUNTER. This counter indicates the number of bits still to be exchange with the Flash Media
card.
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor