MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 309

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

17.5.1
The two I
transmitting data from one of several sources:
Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Audio Clk is typically 11.2896 MHz or 16.93 MHz. Actual value given
Dividers.”
When bit 11 is set, FIFO is in reset condition. The FIFO is always re-set to “1 sample remaining”. The value of the remaining
one sample will be all-zero.
When Philips I
Internal interface is 40 bits / sample (20 left + 20 right). 16, 18 bit words are padded with zeros
LRCK “invert” will invert the incoming LRCK signal between the pin and the serial data receiver and transmitter
SCLK “invert” will invert the incoming SCLK signal between the pin and the serial data receiver and transmitter.
Reset to one sample remaining is used to synchronize the data transfer from one input interface to another output interface
running at the same frequency.
“Zero” means data is transferred at the sampling frequency, with all data cleared down to digital zero.
PDOR1, PDOR2, PDOR3: audio data output registers.
Serial data transmit / receive interfaces have no limit on minimum incoming or outgoing sampling frequency. The maximum
SCLK frequency is limited to 1/3 of the internal system clock (CPUclk/2). Mark/space ratio should be equal or better than
38/62.
Reprogramming bits 15-12 during functional operation is not allowed. Reprogramming is only allowed while FIFO is in reset
condition (bit 11 set ‘1’)
When “digital zero” is selected as the source, the FIFO outputs “zero” on its outgoing data bus, regardless of the input side
and content of the FIFO. No FIFO related exceptions are generated.
When the FIFO leaves the reset state, because the user writes a “normal operation” state into the control register, the FIFO
is kept in reset until the first long-word is written to it. As a result, the “start” of the normal operation is synchronized with
the writing of the first data into the FIFO.
When IIS/Sony interface LRCK/SCLK is set in “follow IIS” mode, the bit clock and word clock become exactly identical to bit
and word clock of the “followed” interface. If e.g. LRCK/SCLK for IIS interface 2 is set in “follow IIS1”, the DAC or ADC
connected to IIS2 can use the bit clock and word clock of IIS1. Note:- Bit and word clock for IIS2 can be used then used as
GPIO if desired.
Bit 16 extends the Tx FIFO control bit and the bit order becomes 16, 10, 9, 8.
These bits should be programmed to zero for normal operation. For IIS1 receiver, it is possible to use the special EF/CFLG
insertion mode, by setting bit 18 = 1. This mode is intended to interface with Philips CD decoders (SAA7324 and successors).
When this mode is used, IIS1CONFIG must be programmed to “Sony” mode, 16 bits. The SAA7324 must also be
programmed to “Sony” mode, 16 bits. The CFLG flag coming from SAA7324 must be connected with CFLG input. The EF
flag coming from SAA7324 must be connected with EF input. If all this is done correctly, the device will receive the 16 MSB
‘s of the incoming data in bits [17:2] of the received serial data. Bit [1] of the received data is the EF flag of the corresponding
word, as output by SAA7324. Bit [1] will be set if the MSB or the LSB or both are flagged. Bit [0] of the received data is the
CFLG flag of the corresponding word, as output by SAA7324. These flags can be used for implementing an electronic shock
protection FIFO.
For IIS4 only the SCLK4 setting can be used. See
function.
SCLK INVERT
•
Field
One of the three processor data out registers.
2
S/EIAJ transmitters operate independently. Each of the transmitters has the capability of
IIS/EIAJ Transmitter Descriptions
2
S mode is selected, 16-18-20 bits will yield the same result.
Table 17-5. IIS Configuration Registers Field Descriptions (continued)
See note 6 following bit these descriptions.
1 Invert on bit clock
0 No invert on bit clock
MCF5253 Reference Manual, Rev. 1
Chapter 12, “Analog to Digital Converter
Description
Table 4-4
in
Chapter 4, “Phase-Locked Loop and Clock
(ADC)”
Audio Interface Module (AIM)
for the purpose of this
17-11