MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 63

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3
ColdFire Core
This chapter provides an overview of the microprocessor core of the MCF5253. The chapter describes the
CF2 memory map and register description as it is implemented on the MCF5253. It also includes a full
description of exception handling, data formats, an instruction set summary, and a table of instruction
timings. For detailed information on instructions, see the ColdFire Family Programmer’s Reference
Manual.
3.1
Figure 3-1
The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The
Instruction Fetch Pipeline (IFP) is responsible for instruction address generation and instruction fetch. The
instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution
Freescale Semiconductor
Processor Pipelines
INSTRUCTION
shows a block diagram of the processor pipelines of a CF2 ColdFire core.
EXECUTION
PIPELINE
OPERAND
PIPELINE
FETCH
OEP
Figure 3-1. CF2 ColdFire Processor Core Pipelines
IFP
INSTRUCTION
ADDRESS IA
GENERATION
DECODE & SELECT,
INSTRUCTION
FETCH
OPERAND FETCH
GENERATION,
INSTRUCTION
MCF5253 Reference Manual, Rev. 1
ADDRESS
EXECUTE
BUFFER
FIFO
3 X 32
DATA[31:0]
ADDRESS[31:0]
3-1