MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 229

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 14
DMA Controller
The direct memory access controller (DMAC) of the MCF5253 quickly and efficiently moves blocks of
data with minimal processor overhead. The DMA module, shown in
that allow byte, word, or longword data transfers. These transfers are dual address to on-chip devices; such
as the ATA, UART, SDRAM controller, and audio module.
14.1
The features of the DMA controller as follows:
14.2
This section contains a brief description of the DMA module signals that provide handshake control for
either a source or destination external device.
Freescale Semiconductor
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Four fully independent programmable DMA controller module channels
Auto-alignment feature for source or destination accesses
Dual-address transfer capability
Channels 0 and 1 request signals may be connected to the audio block
Channels 2 and 3 request signals may be connected to the interrupt lines of UART0 and UART1,
respectively
Any of the four channels request signals may be connected to the ATA module
Channel arbitration on transfer boundaries
Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
Burst and cycle steal transfers
Independent transfer widths for source and destination
Independent source and destination address registers
Data transfer in two clocks
DMA Features
DMA Signal Description
DMA transfers to and from the IDE interface are considered memory to
memory transfers and therefore there are no specific channel allocations
mentioned in this section.
MCF5253 Reference Manual, Rev. 1
Table 14-1
NOTE
summarizes these handshake signals.
Figure
14-1, provides four channels
14-1