MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 427

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 23
Advanced Technology Attachment Controller (ATA)
This chapter discusses the modes of operation, signal descriptions, memory map, register descriptions,
timing parameters, and functional description of the ATA interface.
The ATA interface of the MCF5253 is an AT attachment host interface. Its main use is to interface with
hard disc drives and optical disc drives. It interfaces with the ATA device over a number of ATA signals.
23.1
The ATA interface includes the following features:
23.2
Figure 23-1
Freescale Semiconductor
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Programmable timing on the ATA bus. Works with wide range of bus frequencies.
Compliant with ATA-6 specification
— Supports PIO modes 0, 1, 2, 3, and 4
— Supports multiword DMA modes 0, 1, and 2
— Supports ultra DMA modes 0, 1, 2, and 3 with bus clock of at least 50 MHz
128-byte FIFO part of interface
FIFO receive alarm, FIFO transmit alarm to DMA unit
Zero-wait cycles transfer between DMA bus and FIFO allows fast FIFO reading/writing
Features
Block Diagram
illustrates the block diagram of the ATA interface.
MCF5253 Reference Manual, Rev. 1
23-1