ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 104

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.9
8151H–AVR–02/11
Asynchronous Operation of Timer/Counter0
Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-
When Timer/Counter0 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0.
2. Select clock source by setting AS0 as appropriate.
3. Write new values to TCNT0, OCR0, and TCCR0.
4. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.
5. Clear the Timer/Counter0 interrupt flags.
6. Enable interrupts, if needed.
• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external
• When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a
• When entering Power-save or Extended Standby mode after having written to TCNT0,
Timer/Counter0, the Timer Registers TCNT0, OCR0, and TCCR0 might be corrupted. A safe
procedure for switching clock source is:
clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main
clock frequency must be more than four times the Oscillator frequency.
temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the Temporary Register have been transferred to its
destination. Each of the three mentioned registers have their individual temporary register,
which means that, for example, writing to TCNT0 does not disturb an OCR0 write in progress.
To detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented.
OCR0, or TCCR0, the user must wait until the written register has been updated if
Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter sleep mode
before the changes are effective. This is particularly important if the Output Compare0
interrupt is used to wake up the device, since the output compare function is disabled during
writing to OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode
before the OCR0UB bit returns to zero, the device will never receive a compare match
interrupt, and the MCU will not wake up.
TCNTn
(clk
(CTC)
OCRn
OCFn
clk
clk
I/O
I/O
Tn
/8)
caler (f
clk_I/O
TOP - 1
/8)
TOP
TOP
BOTTOM
ATmega128A
BOTTOM + 1
104