ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 176

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3
8151H–AVR–02/11
Clock Generation
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
The following control bits have changed name, but have same functionality and register location:
The clock generation logic generates the base clock for the transmitter and receiver. The
USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asyn-
chronous, Master Synchronous, and Slave Synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-
ation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using Synchronous mode.
Figure 20-2
Figure 20-2. Clock Generation Logic, Block Diagram
• Transmitter Operation
• Transmit Buffer Functionality
• Receiver Operation
• A second buffer register has been added. The two buffer registers operate as a circular FIFO
• The receiver Shift Register can now act as a third buffer level. This is done by allowing the
• CHR9 is changed to UCSZ2
• OR is changed to DOR
buffer. Therefore the UDR must only be read once for each incoming data! More important is
the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the
data in the receive buffer. Therefore the status bits must always be read before the UDR
Register is read. Otherwise the error status will be lost since the buffer state is lost.
received data to remain in the serial Shift Register (see
full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun
(DOR) error conditions.
DDR_XCK
shows a block diagram of the clock generation logic.
XCK
Pin
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
/ 4
Figure
/ 2
20-1) if the buffer registers are
DDR_XCK
ATmega128A
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
176