ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 188

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.6
20.7.7
20.7.8
8151H–AVR–02/11
Disabling the Receiver
Flushing the Receive Buffer
Asynchronous Clock Recovery
The UPE bit is set if the next character that can be read from the receive buffer had a parIty
Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is
valid until the Receive buffer (UDR) is read.
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the receiver will
no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be
flushed when the receiver is disabled. Remaining data in the buffer will be lost
The receiver buffer FIFO will be flushed when the receiver is disabled, that is, the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is
cleared. The following code example shows how to flush the receive buffer.
Note:
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for normal mode, and 8 times the baud rate for Double Speed mode. The horizon-
tal arrows illustrate the synchronization variation due to the sampling process. Note the larger
time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero
are samples done when the RxD line is idle (that is, no communication activity).
Assembly Code Example
C Code Example
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRA, RXC
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
1. See
The USART includes a clock recovery and a data recovery unit for handling asynchronous
data reception. The clock recovery logic is used for synchronizing the internally generated
baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery
logic samples and low pass filters each incoming bit, thereby improving the noise immunity of
the receiver. The asynchronous reception operational range depends on the accuracy of the
internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
r16, UDR
“About Code Examples” on page
(1)
(1)
8.
ATmega128A
Figure 20-5
188