ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 134

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11 Register Description
15.11.1
15.11.2
8151H–AVR–02/11
TCCR1A - Timer/Counter1 Control Register A
TCCR3A - Timer/Counter3 Control Register A
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting.
the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(PC and PFC PWM)
and ICFn
(CTC and FPWM)
(Update at TOP)
TOVn
TCNTn
TCNTn
OCRnx
as TOP)
(clk
clk
clk
I/O
(FPWM)
I/O
Tn
COM1A1
COM3A1
/8)
(if used
R/W
R/W
7
0
7
0
COM3A0
COM1A0
R/W
R/W
6
0
6
0
TOP - 1
TOP - 1
Old OCRnx Value
COM3B1
COM1B1
R/W
R/W
5
0
5
0
Table 15-2
COM3B0
COM1B0
R/W
R/W
4
0
4
0
TOP
TOP
COM3C1
COM1C1
shows the COMnx1:0 bit functionality when
R/W
R/W
3
0
3
0
COM1C0
COM3C0
R/W
R/W
2
0
clk_I/O
2
0
BOTTOM
TOP - 1
New OCRnx Value
/8)
WGM31
ATmega128A
WGM11
R/W
R/W
1
0
1
0
WGM10
WGM30
BOTTOM + 1
R/W
R/W
0
0
0
0
TOP - 2
TCCR3A
TCCR1A
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