ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 136

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-5.
8151H–AVR–02/11
Mode
10
11
0
1
2
3
4
5
6
7
8
9
WGMn3
0
0
0
0
0
0
0
0
1
1
1
1
Waveform Generation Mode Bit Description
WGMn2
(CTCn)
0
0
0
0
1
1
1
1
0
0
0
0
Table 15-4.
Note:
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes.
COMnA1/COMnB1/
(PWMn1)
WGMn1
COMnC1
1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
0
0
1
1
0
0
1
1
0
0
1
1
COMnA1/COMnB1//COMnC1 is set.
details.
0
0
1
1
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
(PWMn0)
WGMn0
0
1
0
1
0
1
0
1
0
1
0
1
COMnA0/COMnB0/
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and Frequency
Correct
PWM, Phase and Frequency
Correct
PWM, Phase Correct
PWM, Phase Correct
Timer/Counter Mode of
Table
COMnC0
Operation
0
1
0
1
15-5. Modes of operation supported by the Timer/Counter
(See “Modes of Operation” on page
See “Phase Correct PWM Mode” on page 128.
(1)
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
WGMn3:0 = 9 or 11: Toggle OCnA on Compare
Match, OCnB/OCnC disconnected (normal port
operation).
For all other WGMn settings, normal port
operation, OCnA/OCnB/OCnC disconnected.
Clear OCnA/OCnB/OCnC on compare match
when up-counting. Set OCnA/OCnB/OCnC on
compare match when downcounting.
Set OCnA/OCnB/OCnC on compare match when
up-counting. Clear OCnA/OCnB/OCnC on
compare match when downcounting.
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
ICRn
OCRnA
ICRn
OCRnA
TOP
BOTTOM
Immediate
TOP
TOP
TOP
Immediate
BOTTOM
BOTTOM
BOTTOM
BOTTOM
TOP
TOP
OCRn
Update of
ATmega128A
x
at
125.)
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
TOVn Flag
Set on
for more
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