ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 22

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
7.5
7.5.1
7.5.2
8151H–AVR–02/11
I/O Memory
External Memory Interface
Features
Overview
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If a reset occurs while a write oper-
ation is in progress, the write operation will be completed provided that the power supply voltage
is sufficient.
The I/O space definition of the Atmel
page
All ATmega128A I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O registers within the address range $00
- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value
of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction
set section for more details. When using the I/O specific commands IN and OUT, the I/O
addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and
ST instructions, $20 must be added to these addresses. The ATmega128A is a complex micro-
controller with more peripheral units than can be supported within the 64 location reserved in
Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is
replaced with SRAM locations when the ATmega128A is in the ATmega103 compatibility mode.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O register, writing a one back into any flag read as set,
thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
The I/O and peripherals control registers are explained in later sections.
•
•
•
•
With all the features the External Memory Interface provides, it is well suited to operate as an
interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-
display, A/D, and D/A. When the eXternal MEMory (XMEM) is enabled, address space outside
the internal SRAM becomes available using the dedicated External Memory pins (see
1 on page
memory configuration is shown in
Four different wait-state settings (including no wait-state).
Independent wait-state setting for different extErnal Memory sectors (configurable sector size).
The number of bits dedicated to address high byte is selectable.
Bus-keepers on data lines to minimize current consumption (optional).
367.
2,
Table 12-2 on page
73,
Figure
Table 12-8 on page
®
AVR
7-4.
®
ATmega128A is shown in
77, and
Table 12-20 on page
ATmega128A
“Register Summary” on
Figure 1-
85). The
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