ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 217

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21-3.
8151H–AVR–02/11
Status Code
(TWSR)
Prescaler Bits
are 0
$08
$10
$38
$40
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Arbitration lost in SLA+R or
NOT ACK bit
SLA+R has been transmitted;
ACK has been received
Status Codes for Master Receiver Mode
Figure 21-14. Formats and States in the Master Receiver Mode
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
Application Software Response
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
From master to slave
From slave to master
$08
S
SLA
To TWCR
STA
0
0
0
0
1
0
0
R
MR
A or A
DATA
$40
$48
$38
$68
A
A
A
STO
0
0
0
0
0
0
0
$78
Other master
Other master
n
continues
continues
P
TWIN
$B0
T
1
1
1
1
1
1
1
DATA
A
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
TWE
A
X
X
X
X
X
0
1
$50
$38
To corresponding
states in slave mode
A
A
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to master transmitter mode
Two-wire Serial Bus will be released and not ad-
dressed slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Other master
DATA
continues
$58
A
ATmega128A
$10
P
R
S
SLA
W
R
MT
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