ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 15

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.8
8151H–AVR–02/11
Reset and Interrupt Handling
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-5.
The Atmel
reset vector each have a separate program vector in the program memory space. All interrupts
are assigned individual enable bits which must be written logic one together with the Global
Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Pro-
gram Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or
BLB12 are programmed. This feature improves software security. See the section
gramming” on page 291
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The interrupt vectors can be moved to the start of the boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to
The Reset vector can also be moved to the start of the boot Flash section by programming the
BOOTRST fuse, see
277.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector
®
shows the internal timing concept for the Register file. In a single clock cycle an ALU
AVR
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
®
Result Write Back
provides several different interrupt sources. These interrupts and the separate
“Boot Loader Support – Read-While-Write Self-Programming” on page
for details.
clk
clk
CPU
CPU
T1
T1
“Interrupts” on page 59
T2
T2
“Interrupts” on page
T3
T3
ATmega128A
for more information.
T4
T4
59. The list also
“Memory Pro-
15