ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 145

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers
16.1
16.2
16.3
8151H–AVR–02/11
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler module, but
the Timer/Counters can have different prescaler settings. The description below applies to all of
the mentioned Timer/Counters.
The Timer/Counter can be clocked directly by the System Clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, that is, operates independently of the clock select logic of the
Timer/Counter, and it is shared by Timer/Counter1, Timer/Counter2, and Timer/Counter3. Since
the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of prescaling arti-
facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also use prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clk
tion logic. The synchronized (sampled) signal is then passed through the edge detector.
16-1
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
tive (CSn2:0 = 6) edge it detects.
Figure 16-1. Tn Pin Sampling
CLK_I/O
T1
shows a functional equivalent block diagram of the Tn synchronization and edge detector
/clk
clk
/256, or f
Tn
I/O
T2
/clk
T3
CLK_I/O
). The Tn pin is sampled once every system clock cycle by the pin synchroniza-
D Q
LE
/1024.
Synchronization
CLK_I/O
D Q
). Alternatively, one of four taps from the prescaler can be used
T1
/clk
T
2
/clk
T
3
pulse for each positive (CSn2:0 = 7) or nega-
D
Q
Edge Detector
ATmega128A
CLK_I/O
clk
/8, f
Tn_sync
(To Clock
Select Logic)
I/O
). The latch
CLK_I/O
Figure
/64,
145