ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 141

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11.16 ICR3H and ICR3L - Input Capture Register 3
15.11.17 TIMSK - Timer/Counter Interrupt Mask Register
8151H–AVR–02/11
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-
ture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding interrupt
vector
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match Interrupt is enabled. The corresponding
interrupt vector (see “Interrupts” on page 59) is executed when the OCF1A flag, located in TIFR,
is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match Interrupt is enabled. The corresponding
interrupt vector (see “Interrupts” on page 59) is executed when the OCF1B flag, located in TIFR,
is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding interrupt vector
(see “Interrupts” on page 59) is executed when the TOV1 flag, located in TIFR, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer sections.
See “Accessing 16-bit Registers” on page 115.
OCIE2
R/W
R/W
7
0
7
0
TOIE2
R/W
R/W
6
0
6
0
59.) is executed when the ICF1 flag, located in TIFR, is set.
TICIE1
R/W
R/W
5
0
5
0
OCIE1A
R/W
R/W
4
0
4
0
ICR3[15:8]
ICR3[7:0]
OCIE1B
R/W
R/W
3
0
3
0
TOIE1
R/W
R/W
2
0
2
0
OCIE0
ATmega128A
R/W
R/W
1
0
1
0
TOIE0
R/W
R/W
0
0
0
0
ICR3H
ICR3L
TIMSK
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