ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 256

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.11 Data Registers
24.11.1
24.11.2
24.11.2.1
8151H–AVR–02/11
Bypass Register
Device Identification Register
Version
ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have
the AVR device in reset during Test mode. If not reset, inputs to the device may be determined
by the scan operations, and the internal software may be in an undetermined state when exiting
the Test mode. Entering Reset, the outputs of any Port Pin will instantly enter the high imped-
ance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be
issued to make the shortest possible scan chain through the device. The device can be set in
the Reset state either by pulling the external RESET pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
The JTAGEN fuse must be programmed and the JTD bit in the I/O register MCUCSR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
The data registers relevant for Boundary-scan operations are:
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
Figure 24-3
Figure 24-3. The Format of the Device Identification Register
Version is a 4-bit number identifying the revision of the component. The JTAG version number
follows the revision of the device, and wraps around at revision P (0xF). Revision A and Q is
0x0, revision B and R is 0x1 and so on.
Bit
Device ID
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain
shows the structure of the Device Identification Register.
MSB
31
Version
4 bits
28
27
Part Number
16 bits
12
11
Manufacturer ID
ATmega128A
11 bits
1
1-bit
LSB
1
0
256