ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 308

IC MCU AVR 128K FLASH 64TQFP

ATMEGA128A-ANR

Manufacturer Part Number
ATMEGA128A-ANR
Description
IC MCU AVR 128K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-ANR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number:
ATMEGA128A-ANR
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10 000
26.8.4
26.9
26.9.1
8151H–AVR–02/11
Programming Via the JTAG Interface
SPI Serial Programming Characteristics
Programming Specific JTAG Instructions
For characteristics of the SPI module, see
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the Reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is
default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be
cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit
will be cleared after two chip clocks, and the JTAG pins are available for programming. This pro-
vides a means of using the JTAG pins as normal port pins in running mode while still allowing In-
System Programming via the JTAG interface. Note that this technique can not be used when
using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must
be dedicated for this purpose.
As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.
The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
Figure
26-9.
“SPI Timing Characteristics” on page
ATmega128A
328.
308

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