ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 304

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.8
26.8.1
8151H–AVR–02/11
SPI Serial Programming Pin Mapping
SPI Serial Programming Algorithm
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important
difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not
used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-
ming mode as shown in
Table 26-13. Pin Mapping SPI Serial Programming
Figure 26-7. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-
tion. The Chip Erase operation turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega128A, data is clocked on the rising edge of SCK.
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
2. V
MISO (PDO)
MOSI (PDI)
XTAL1 pin.
Symbol
CC
SCK
- 0.3V < AVCC < V
Table
PDO
SCK
PDI
26-13.
ck
ck
CC
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 2.7V - 5.5V.
Pins
PE0
PE1
PB1
PE0
PE1
PB1
XTAL1
RESET
GND
(1)
I/O
O
I
I
AVCC
VCC
+2.7 - 5.5V
+2.7 - 5.5V
ck
ck
ATmega128A
≥ 12MHz
≥ 12MHz
(2)
Serial data out
Serial data in
Description
Serial clock
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