ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 224

• Manufacturer Part Number: ATMEGA128A-ANR
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.7.5
Table 21-6.
21.7.6
8151H–AVR–02/11
Status Code
(TWSR)
Prescaler Bits
are 0
$F8
$00
Miscellaneous States
Combining Several TWI Modes
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Miscellaneous States
Figure 21-17. Formats and States in the Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state, see
Status $F8 indicates that no relevant information is available because the TWINT flag is not set.
This occurs between other states, and when the TWI is not involved in a serial transfer.
Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR
are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated
2. The EEPROM must be instructed what location should be read
3. The reading must be performed
4. The transfer must be finished
Reception of the
own slave address
and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
Application Software Response
To/from TWDR
No TWDR action
No TWDR action
From master to slave
From slave to master
S
SLA
To TWCR
STA
No TWCR action
0
R
DATA
STO
1
$A8
$B0
A
A
n
TWIN
T
1
A
TWE
DATA
A
X
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
$B8
A
Next Action Taken by TWI Hardware
DATA
ATmega128A
$C0
$C8
A
A
P or S
All 1's
Table
P or S
21-6.
224