XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 139

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.4 Phase-Locked Loop (PLL)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
INT ECLK
CANCLK
T1CLK
T2CLK
T3CLK
T4CLK
PCLK
XCLK
NOTE:
The phase-locked loop (PLL) of the MC68HC912D60A is designed for
robust operation in an Automotive environment. The allowed PLL crystal
or ceramic resonator reference of 0.5 to 8MHz is selected for the wide
availability of components with good stability over the automotive
temperature range. Please refer to
Chains
When selecting a crystal, it is recommended to use one with the lowest
possible frequency in order to minimise EMC emissions.
An oscillator design with reduced power consumption allows for slow
wait operation with a typical power supply current less than a milli-
ampere. The PLL circuitry can be bypassed when the VDDPLL supply is
at VSS level. In this case, the PLL module is powered down and the
oscillator output transistor has a stronger transconductance for improved
drive of higher frequency resonators (as the crystal frequency needs to
be twice the maximum bus frequency). Refer to
Signal
Figure 11-1. Internal Clock Relationships
Descriptions.
for an overview of system clocks.
Clock Functions
Figure 11-6
Figure 3-5
in section
Phase-Locked Loop (PLL)
Clock Divider
Clock Functions
in
Technical Data
Pinout and
139

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