XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 352

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Analog-to-Digital Converter
18.4 Functional Description
18.4.1 Analog Input Multiplexer
18.4.2 Sample Buffer Amplifier
Technical Data
352
NOTE:
The MCU can discover when result data is available in the result
registers with an interrupt on sequence complete or by polling the
conversion complete flags
ATD conversion modes should not be confused with MCU operating
modes such as STOP, WAIT, IDLE, RUN, DEBUG, and SPECIAL (test)
modes or with module defined operating modes such as power down,
fast flag clear, 8-bit resolution, 10-bit resolution, interrupt enable, clock
prescaler setting, and freeze modes; and finally do not confuse with
module result data formats such as right justify mode and left justify
mode.
The analog input multiplexer selects one of the 8 external analog input
channels to generate an analog sample. The input analog signals are
unipolar and must fall within the potential range of VSSA to VDDA
(analog electronics supply potentials).
A sample amplifier is used to buffer the input analog signal so that a
storage node can be quickly charged to the sample potential.
WAIT is executed (if the ASWAI bit is activated)
STOP is executed.
The SCF bit is set after the completion of each sequence.
The CCF bit associated with each result register is set when that
register is loaded with result data.
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor

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